EP2SGX60EF1152C4N vs EP2SGX60EF1152I3 对比

详细并排对比 EP2SGX60EF1152C4N 出自 Altera 和 EP2SGX60EF1152I3 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP2SGX60EF1152C4N EP2SGX60EF1152C4N - Stratix II GX 60K FPGA, 1152-BGA | Altera

EP2SGX60EF1152C4N - Stratix II GX 60K FPGA, 1152-BGA | Altera

EP2SGX60EF1152C4N ⚠ 最后一次采购

规格对比

参数 EP2SGX60EF1152C4N EP2SGX60EF1152I3
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $1,350.00 $365.00
Series Stratix II GX EP2SGX60
Family Stratix II GX FPGA Stratix II GX
Logic Elements 60,440 —
LABs / CLBs 3,022 —
Total Memory Bits 2,544,192 —
Maximum User I/O 534 —
Number of I/O Banks 12 —
High-Speed Transceivers Up to 12 channels —
Transceiver Data Rate (max) 6.375 Gbps per channel —
Core Voltage 1.2 V —
工作温度 0C to +85C (Commercial) -40C to +100C (Industrial, I3 speed grade)
安装类型 Surface Mount Surface Mount (BGA)
封装 1152-BBGA (FBGA-1152), 35x35 mm, 1.0 mm pitch 1152-ball FBGA, 35 mm x 35 mm, 1 mm pitch
RoHS 状态 Compliant (lead-free, MS-034AAR-1) [DATA_NEEDED: not in retrieved snippets]
Process Technology 90 nm CMOS 90 nm CMOS
Design Software Altera Quartus II (7.2 - 13.0sp1) —
Logic Elements (LEs) — 60,440
Adaptive Logic Modules (ALMs) — 30,220 (estimated from LEs)
Equivalent Logic Cells (CLBs) — 60,440
Embedded Memory (Bits) — 2,544,192 bits (per DigiKey listing for the I4N variant)
Maximum Internal Frequency — 717 MHz
Combinational Delay (per CLB) — 2.99 ns
Multi-Gigabit Transceivers — [DATA_NEEDED: exact count for EP2SGX60]
Maximum Transceiver Data Rate — 6.375 Gbps (per Stratix II GX family spec)
Total RAM Bits — 2,544,192 bits
Pin/Ball Count — 1152
Speed Grade — I3 (Industrial)
Configuration Mode — Enhanced (EPC) - fast parallel via external memory

数据手册与资源

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