EP2SGX60FF1152 vs EP2SGX60EF1152C4N 对比
详细并排对比 EP2SGX60FF1152 出自 Altera 和 EP2SGX60EF1152C4N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2SGX60FF1152 | EP2SGX60EF1152C4N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,950.00 | $1,350.00 |
| Series | Stratix II GX | Stratix II GX |
| Family | Stratix II GX FPGA | Stratix II GX FPGA |
| Logic Elements | 60,440 | 60,440 |
| Embedded Memory | 2,544,192 bits | — |
| DSP Blocks (18x18 Multipliers) | 192 (16 blocks) | — |
| Maximum User I/O | 364 | 534 |
| Number of LABs/CLBs | 3022 | — |
| Transceivers | 12 channels up to 3.125 Gbps | — |
| 封装 | 1152-BBGA, FineLine BGA (FF1152) | 1152-BBGA (FBGA-1152), 35x35 mm, 1.0 mm pitch |
| 工作温度 | -40C to +85C (industrial) | 0C to +85C (Commercial) |
| Voltage - Supply | 1.2 V core / multiple VCCIO rails | — |
| 安装类型 | Surface Mount | Surface Mount |
| Process Technology | 90 nm CMOS, SRAM-based | 90 nm CMOS |
| Configuration Method | JTAG IEEE 1149.1, Serial, Passive Parallel, Fast Passive Parallel | — |
| RoHS 状态 | Compliant | Compliant (lead-free, MS-034AAR-1) |
| LABs / CLBs | — | 3,022 |
| Total Memory Bits | — | 2,544,192 |
| Number of I/O Banks | — | 12 |
| High-Speed Transceivers | — | Up to 12 channels |
| Transceiver Data Rate (max) | — | 6.375 Gbps per channel |
| Core Voltage | — | 1.2 V |
| Design Software | — | Altera Quartus II (7.2 - 13.0sp1) |