EP3CLS100U484I7N vs EP3CLS100F484I7N 对比
详细并排对比 EP3CLS100U484I7N 出自 Altera 和 EP3CLS100F484I7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP3CLS100U484I7N | EP3CLS100F484I7N |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $108.00 | $67.90 |
| Device Family | Cyclone III LS | — |
| Series | Cyclone III | — |
| Logic Elements (LE) | 100,448 | 100,448 |
| Total RAM Bits | 4,451,328 bits (~4.4 Mbit) | — |
| Maximum User I/O | 278 | — |
| Number of LABs | 6,278 | — |
| DSP Blocks | 24 (18x18 multipliers) | — |
| Embedded Memory | 432 M9K blocks (9 Kbit each) | 4,451,328 bits (M9K blocks) |
| PLLs | 4 | 4 |
| Core Supply Voltage | 1.2 V | — |
| I/O Supply Voltage | 1.2 V to 3.3 V (per bank) | — |
| 封装 | 484-FBGA (UBGA) | 484-ball FBGA (F484) |
| 工作温度 | -40C to +100C (Industrial, 'I') | — |
| Process Technology | TSMC 65 nm low-power (LP) | 65 nm CMOS |
| 安装类型 | Surface Mount | — |
| Security Features | AES-128 bit-stream encryption, JTAG disable, tamper detection | — |
| RoHS 状态 | Compliant | — |
| MSL 等级 | 3 (168 hours) | — |
| Family | — | Cyclone III LS |
| Device Type | — | FPGA - Field Programmable Gate Array |
| Logic Array Blocks (LAB) | — | 6,278 |
| 18x18 Multipliers | — | 278 |
| User I/O Pins (max) | — | 294 |
| Core Supply Voltage (VCCINT) | — | 1.2 V |
| Maximum Internal Frequency | — | 437.5 MHz |
| Operating Temperature (Industrial) | — | -40 °C to +100 °C |
| Speed Grade | — | 7 (medium) |
| Configuration Modes | — | AS, PS, JTAG, FPP |
| Lead-Free / RoHS | — | Yes (LEAD FREE per FindIC) |