EP3SE50F484C3N vs EP3SE50F484C3 对比

详细并排对比 EP3SE50F484C3N 出自 Intel 和 EP3SE50F484C3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SE50F484C3N EP3SE50F484C3
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $832.10 $820.00
Family Stratix III E —
Device Logic Elements 47,500 —
Logic Array Blocks (LABs) 1,900 —
Adaptive Logic Modules (ALMs) 18,750 —
Embedded Memory (Bits) 5,760,000 —
User I/Os 296 296
Maximum Internal Frequency 717 MHz (typical); 800 MHz per DigChip —
Process Technology TSMC 40 nm low-power CMOS 40 nm TSMC
封装 484-ball FBGA (FCBGA), 1.0 mm pitch 484-ball FBGA (FineLine BGA)
电源电压 Core and I/O voltages per Stratix III E datasheet —
工作温度 0C to +85 C (commercial, C suffix) 0C to 85C (Commercial)
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 3 (per JEDEC J-STD-020 for FCBGA packages) [DATA_NEEDED: moisture sensitivity level]
RoHS 状态 Lead-free (per DigiKey listing) —
Configuration Mode Passive Serial, Fast Passive Parallel, Fast Active Serial, JTAG —
Design Software Intel Quartus II (Stratix III support) —
生命周期状态 Obsolete (per Worldway listing 2026-04-05) —
Device Family — Stratix III E (Enhanced)
Logic Elements (LE) — 47,500
Adaptive Logic Modules (ALM) — 19,000
Embedded Memory (M9K + M144K) — 5,760 Kbits
DSP Blocks (18x18 multipliers) — 384
User I/O Banks — [DATA_NEEDED: number of user I/O banks]
High-Speed Transceivers — [DATA_NEEDED: package-dependent count for 484-FBGA]
Internal Operating Frequency — Up to 800 MHz
Speed Grade — C3 (mid)
Supply Voltage (Core) — [DATA_NEEDED: nominal core voltage]
Configuration Modes — AS, PS, FPP, JTAG
Lead-Free / RoHS — [DATA_NEEDED: lead-free / RoHS status from manufacturer]

数据手册与资源

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