EP3SL200H780C3N vs EP3SE260H780C3N 对比

详细并排对比 EP3SL200H780C3N 出自 Intel 和 EP3SE260H780C3N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL200H780C3N EP3SE260H780C3N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $4,995.00 $1,325.00
Family Stratix III L (low-power) —
Process Node 40 nm —
Logic Elements 200,000 —
Embedded Memory Bits 10,901,504 bits —
Logic Array Blocks (LABs) 8,000 —
User I/Os 488 488
封装 780-Ball FCBGA (HBGA), 29 x 29 mm 780-BBGA, FCBGA (H780)
安装类型 Surface Mount Surface Mount
Maximum Internal Clock Frequency 800 MHz —
Transceivers 24 channels, up to 3.75 Gbps [DATA_NEEDED: number of embedded transceivers and max data rate]
DSP Blocks 384 [DATA_NEEDED: number of DSP blocks and precision]
Speed Grade C3 (commercial, -3 speed) —
工作温度 0C to +85C (commercial) 0 °C to +85 °C (C grade, commercial)
Voltage - Core 0.9 V / 1.0 V (core, VCC) —
Voltage - I/O 1.2 V to 3.3 V (VCCIO banks) —
MSL 等级 3 —
Lead-Free / RoHS Yes —
Mounting Pitch 1.0 mm ball pitch —
PLLs 12 (Stratix III PLL array) —
Configuration JTAG IEEE Std 1149.1, passive/active serial —
Series — Stratix® III E
Logic Elements (LE) — 255,000
Embedded Memory (bits) — 16,672,768
Number of LABs/CLBs — 10,200
Number of Pins / Balls — 780
Process Technology — 40 nm CMOS
Maximum Core Frequency — [DATA_NEEDED: maximum core frequency MHz]
Supply Voltage (VCCINT) — [DATA_NEEDED: VCCINT nominal V]
RoHS 状态 — Compliant (lead-free 'N' suffix)
湿敏等级(MSL) — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Configuration Method — SRAM-based, configured via JTAG / passive / active serial / fast passive parallel
Design Toolchain — Altera Quartus II (legacy); Intel Quartus Prime

数据手册与资源

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