EP3SL340H1152C4L vs EP3SL340H1152I4L 对比

详细并排对比 EP3SL340H1152C4L 出自 Altera 和 EP3SL340H1152I4L 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL340H1152C4L EP3SL340H1152I4L
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $3,500.00 $4,100.00
Series Stratix III L —
Logic Elements 337,500 337,500
Embedded Memory Bits 18,822,144 —
Maximum User I/O 744 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] 13,500
Embedded 18x18 Multipliers 384 (per family datasheet) —
Process Technology 65 nm —
Core Voltage (VCCINT) 1.1 V —
工作温度 0 C to +85 C (commercial) -40C to +100C (industrial)
Speed Grade C4L (L-suffix low power) 4
封装 1152-BBGA, FCBGA (HBGA) 1152-ball FC-HFBGA (FCBGA)
安装类型 Surface Mount (BGA) Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant (per Intel/Altera product page)
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] —
Configuration Memory SRAM-based, volatile (needs external config device) —
Maximum Operating Frequency [DATA_NEEDED: per design, ~450 MHz logic per GlobalSpec listing] —
I/O Standards Supported LVDS, LVTTL, LVCMOS, SSTL, HSTL (per family) —
Family — Stratix III L
Adaptive Logic Modules (ALMs) — [DATA_NEEDED: ALM count]
Total Memory Bits — 18,221,440 bits
Embedded Memory — M9K + M144K blocks
DSP Blocks (18x18 Multipliers) — [DATA_NEEDED: multiplier count]
User I/O Pins — 744
User I/O Banks — [DATA_NEEDED: I/O bank count]
Process Node — 65 nm
Core Voltage — 0.9 V
PLLs — [DATA_NEEDED: PLL count]
High-Speed Transceivers — [DATA_NEEDED: transceiver count]
JTAG Support — IEEE Std 1149.1 boundary-scan
Configuration — FPGA, SRAM-based, in-system programmable
Lead-Free — Yes (Pb-free BGA balls)

数据手册与资源

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