EP3SL50F484I4 vs EP3SL50F484I4L 对比

详细并排对比 EP3SL50F484I4 出自 Intel 和 EP3SL50F484I4L 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL50F484I4 EP3SL50F484I4L
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $558.00 $658.26
Device Family Stratix III L —
Logic Elements (LE) 47,500 47,500
Logic Array Blocks (LABs) 1,900 —
Embedded Memory Bits 2,184,192 bits 2,184,192 bits (~273 KB)
Maximum User I/O 296 —
Process Technology 65 nm CMOS 65 nm low-power CMOS
Internal Frequency 800 MHz (max, per digchip datasheet summary) —
Core Supply Voltage 1.1 V —
封装 484-ball FC-FBGA (FCBGA, 1.0 mm pitch) 484-ball FBGA (FCBGA)
工作温度 -40C to +100C (industrial) 0 °C to 85 °C (commercial, per DigiKey listing)
Grade Suffix I4 = Industrial, speed grade 4 —
Configuration Modes JTAG, Passive Serial, FPP, PPA Passive Serial, Fast Passive Parallel, JTAG
MultiTrack Interconnect Yes —
TriMatrix Embedded Memory MLAB, M9K, M144K blocks —
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 3 (168 hours) —
RoHS 状态 Compliant —
Lead-Free Yes —
Series — Stratix III L (Low Power)
Family — Stratix III
User I/O Pins — 296
Speed Grade — 4
电源电压 — 0.9 V core (family-typical)
Lead-Free / RoHS — Yes (RoHS compliant)
Transceivers — Family supports up to 4 transceivers per family datasheet
DSP Blocks — Family supports up to 384 18x18 multipliers (family-level)

数据手册与资源

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