EP3SL50F484I4G vs EP3SL50F484I4L 对比

详细并排对比 EP3SL50F484I4G 出自 Intel 和 EP3SL50F484I4L 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP3SL50F484I4G EP3SL50F484I4L
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $165.00 $658.26
Family Stratix III L Stratix III
Logic Elements 47,500 —
LABs/CLBs 1,900 —
Total Memory Bits 2,184,192 bits —
Number of I/O 296 user I/O —
Number of Logic Gates [DATA_NEEDED: total gate count] —
Core Voltage 1.1 V —
Process Technology 65 nm CMOS 65 nm low-power CMOS
Maximum Internal Frequency 450 MHz —
工作温度 -40C to +100C (Industrial) 0 °C to 85 °C (commercial, per DigiKey listing)
封装 484-BBGA, FC-BGA (FineLine BGA) 23 x 23 mm 484-ball FBGA (FCBGA)
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant —
Supply Voltage Range [DATA_NEEDED: full supply tolerance band] —
Configuration Method SRAM-based, loaded via JTAG, Active Serial, or Active Parallel —
Series — Stratix III L (Low Power)
Logic Elements (LE) — 47,500
Embedded Memory Bits — 2,184,192 bits (~273 KB)
User I/O Pins — 296
Speed Grade — 4
电源电压 — 0.9 V core (family-typical)
Lead-Free / RoHS — Yes (RoHS compliant)
Configuration Modes — Passive Serial, Fast Passive Parallel, JTAG
Transceivers — Family supports up to 4 transceivers per family datasheet
DSP Blocks — Family supports up to 384 18x18 multipliers (family-level)

数据手册与资源

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