EP610DC-30 vs EP610DC-15 对比
详细并排对比 EP610DC-30 出自 Altera 和 EP610DC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610DC-30 | EP610DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.40 | $7.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | 4 |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 15 ns (speed grade -15) |
| Dedicated Inputs | 16 | 20 |
| I/O Pins | 16 (with output enable) | — |
| 封装 | 24-pin CERDIP (windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 安装类型 | Through-Hole | Through-Hole |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | CMOS |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 工作温度 | Commercial (0C to +70C) | 0C to 70C (commercial) |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Method | — | JEDEC fuse map, UV erasure |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |