EP610PI-30 vs EP610JI-30 对比

详细并排对比 EP610PI-30 出自 Rochester Electronics 和 EP610JI-30 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Rochester Electronics
EP610PI-30 EP610PI-30 - 16-Macrocell Classic EPLD, 30ns, PDIP-24

EP610PI-30 - 16-Macrocell Classic EPLD, 30ns, PDIP-24

EP610PI-30 ⚠ 最后一次采购

规格对比

参数 EP610PI-30 EP610JI-30
品牌 Rochester Electronics Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.85 $9.40
Family EP610 Classic EPLD Altera Classic EPLD (EP610)
Logic Elements / Macrocells 16 macrocells —
Usable Gates 300 gates —
Propagation Delay (tPD) 30 ns (PI-30 speed grade) —
Maximum Frequency (pipelined) 100 MHz —
Process Technology CMOS EEPROM CMOS
Supply Voltage (VCC) 5 V —
引脚数 24 —
封装 PDIP-24 (Plastic DIP) CQCC28 (windowed ceramic JLCC, J-bend)
Number of Global Clocks 2 —
Number of Dedicated Inputs 4 —
Number of I/O Pins 10 —
Programming Technology EEPROM (in-system, 100+ cycles) —
工作温度 [DATA_NEEDED: operating temperature range] -40C to +85C (industrial, per EP610 family suffix convention)
RoHS 状态 Not Compliant (per distributor data) [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
ECCN EAR99 —
HTS Code 8542.39.00.01 —
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 16
Propagation Delay (tpd) — 30 ns (max)
Pipelined Data Rate — Up to 100 MHz
Product Terms — 160
Dedicated Inputs — 4
I/O Pins — 16
External Clocks — 2
电源电压 — 5 V (single supply)
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
安装类型 — Surface Mount (JLCC)
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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