EP910DC-40 vs EP910DC-30 对比
详细并排对比 EP910DC-40 出自 Altera 和 EP910DC-30 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910DC-40 | EP910DC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.95 | $15.60 |
| Device Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND/OR, UV-erasable CMOS | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| Bidirectional I/O Pins | 24 | — |
| Total Inputs to Logic Array | 36 | — |
| Product Terms | 240 maximum | — |
| Maximum Propagation Delay (tPD) | 40 ns | — |
| Maximum Operating Frequency (fMAX) | 25 MHz | — |
| Global Clocks | 2 | — |
| 电源电压 | 5 V (typical for Classic EPLD family) | 5 V |
| Operating Temperature (Commercial) | 0 °C to 70 °C | — |
| 封装 | DIP-40 (ceramic, through-hole) | DIP-40 (through-hole, 600 mil) |
| 安装类型 | Through-Hole | Through-Hole |
| RoHS 状态 | [DATA_NEEDED: rohs_status] | — |
| Programming Method | UV-erase + EPROM programmer; on-board logic test circuitry | UV-Erasable / OTP |
| Family | — | Classic EPLD (EP910 series) |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Process Technology | — | CMOS |
| 工作温度 | — | 0C to +70C (commercial) |