EP910ILI-25 vs EP910DC-30 对比
详细并排对比 EP910ILI-25 出自 Altera 和 EP910DC-30 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910ILI-25 | EP910DC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.25 | $15.60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | 30 ns (max) |
| Technology | CMOS, EPROM | — |
| Architecture | PAL-type with global interconnect bus | PAL-type AND-OR sum-of-products, CMOS |
| 封装 | PLCC-44 (windowed ceramic, J-lead) | DIP-40 (through-hole, 600 mil) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| 工作温度 | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | UV-Erasable / OTP |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| RoHS 状态 | Non-compliant (windowed ceramic package) | — |
| Family | — | Classic EPLD (EP910 series) |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| 电源电压 | — | 5 V |
| Process Technology | — | CMOS |
| 安装类型 | — | Through-Hole |