EPC164C88N vs EPC16JC88 对比
详细并排对比 EPC164C88N 出自 Intel 和 EPC16JC88 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC164C88N | EPC16JC88 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | Memory ICs | Memory ICs |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.20 | $17.95 |
| 功能 | In-system programmable configuration PROM for SRAM-based FPGAs | — |
| Memory Density | 16 Mbit | — |
| Configuration Interface | Altera passive serial / fast passive parallel | Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO |
| Operating Voltage (VCCINT) | 3.3 V typical | — |
| Supported FPGA Voltages | 1.8 V, 2.5 V, 3.3 V, 5.0 V | — |
| 封装 | 88-pin UBGA (Ultra FineLine BGA) 11x8 mm | 88-ball UBGA (11 x 8 mm), JEDEC designation C88 |
| 安装类型 | Surface Mount (BGA) | — |
| 工作温度范围 | [DATA_NEEDED: industrial or commercial grade] | — |
| MSL 等级 | [DATA_NEEDED: MSL classification] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance declaration] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free finish] |
| REACH Status | [DATA_NEEDED: REACH compliance] | — |
| Compatible FPGA Families | Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix GX, Stratix II GX, HardCopy II | — |
| Configuration Mode | Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| Reprogrammability | Yes (in-system via JTAG) | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Family | — | Enhanced Configuration Device (EPC4 / EPC8 / EPC16) |
| Device Function | — | In-system programmable configuration PROM for SRAM-based FPGAs |
| Density | — | 16 Mbit |
| Programmability | — | In-system programmable via IEEE 1149.1 JTAG |
| Operating Temperature Grade | — | Industrial (J suffix) |
| 电源电压 | — | [DATA_NEEDED: VCC operating range] |
| Supported FPGA Families | — | Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface) |
| Configuration Clock | — | Driven by target FPGA during configuration |
| Multi-Device Configuration | — | Supports daisy-chain configuration of multiple FPGAs |
| 湿敏等级（MSL） | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| 无卤 | — | [DATA_NEEDED: halogen-free status] |