EPC16QC-100T vs EPC16QC100II 对比

详细并排对比 EPC16QC-100T 出自 Altera 和 EPC16QC100II 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16QC-100T EPC16QC100II
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $14.50 $10.75
存储器类型 Flash Configuration PROM (in-system programmable) FPGA Configuration PROM (Flash-based)
Memory Density 16 Mbit (2 Mbyte) 16 Mbit
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone
Configuration Data Width 8-bit or 16-bit (cascaded dual-device mode) —
Configuration Modes Serial (single device), Parallel (two cascaded devices) —
Data Compression Support Yes (35% to 55% bitstream reduction typical) —
JTAG / Boundary Scan IEEE 1149.1 compliant, in-system programmable —
电源电压 3.3 V —
封装 100-pin PQFP (20 x 14 mm), 0.65 mm pitch 100-pin PQFP (Plastic Quad Flat Pack)
工作温度 [DATA_NEEDED: Operating temperature range] -40C to +85C (Industrial)
Cascade Interface nCE / nOE handshake for multi-device chains —
Programming Interface JTAG (IEEE 1149.1) and serial —
Endurance [DATA_NEEDED: Program/erase cycle rating] —
Data Retention [DATA_NEEDED: Data retention specification] —
RoHS 状态 unknown Compliant
Lead-Free unknown —
MSL 等级 [DATA_NEEDED: Moisture sensitivity level] 3 (per JEDEC J-STD-020)
安装类型 Surface Mount —
Configuration Mode — FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous)
Programmability — In-System Programmable via IEEE 1149.1 (JTAG)
Cascade Support — Yes (multi-PROM cascading supported)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant configuration pins
Package Dimensions — 20 mm x 14 mm, 0.5 mm pitch
Lead Finish — Matte Tin (lead-free)
Configuration Pins — DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE
Compression Support — Yes (reduces on-PROM footprint vs uncompressed bitstream)

数据手册与资源

浏览全部产品 创建 BOM 获取报价