EPC16QC100N vs EPC16QC100T 对比

详细并排对比 EPC16QC100N 出自 Altera 和 EPC16QC100T 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16QC100N EPC16QC100T
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $24.10 $17.95
存储容量 16 Mbit (16,777,216 bits) 16 Mbit
Programmable Type In System Programmable —
Configuration Clock Frequency 33 MHz max —
On-Chip Decompression Yes (supports compressed bitstreams) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.3 V
Access Time 90 ns typical [DATA_NEEDED: serial access time]
Flash Read Bandwidth 160 Mbps (16-bit DQ at 10 MHz) —
Configuration Interface FPP / PS / AS via dedicated FPGA pins —
JTAG (IEEE 1149.1) ISP Supported —
工作温度 0 C to 70 C 0C to +70C (commercial)
封装 100-pin PQFP (20 x 14 mm) PQFP-100 (20 x 14 mm)
安装类型 Surface Mount Surface Mount
Lead Free Yes (per datasheet) —
Packaging Tray —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
存储器类型 — In-System Programmable Configuration PROM
接口 — Serial FPGA configuration + JTAG (IEEE 1149.1)
Programmability — In-System Programmable via JTAG
Daisy-Chain Support — Yes (multi-device cascade)
Data Compression — Built-in decompression engine (up to 35% expansion)
FPGA Compatibility — Altera Cyclone, Stratix, ACEX, APEX series
Lead-Free / RoHS — Depends on date code; verify per lot
MSL 等级 — 3 (per JEDEC J-STD-020)
Programming Cycles — 100 typical (per Altera datasheet)
Packaging Suffix — 'T' indicates Tape and Reel
Max DCLK Frequency — [DATA_NEEDED: max DCLK frequency]

数据手册与资源

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