EPC16QC100T vs EPC16C100T 对比
详细并排对比 EPC16QC100T 出自 Altera 和 EPC16C100T 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC16QC100T | EPC16C100T |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | Memory ICs | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.95 | $16.20 |
| 存储器类型 | In-System Programmable Configuration PROM | — |
| 存储容量 | 16 Mbit | 16 Mb |
| 接口 | Serial FPGA configuration + JTAG (IEEE 1149.1) | Serial / Parallel / JTAG (IEEE 1149.1) |
| Supply Voltage (VCC) | 3.3 V | — |
| Programmability | In-System Programmable via JTAG | In-system via JTAG |
| Daisy-Chain Support | Yes (multi-device cascade) | — |
| Data Compression | Built-in decompression engine (up to 35% expansion) | — |
| FPGA Compatibility | Altera Cyclone, Stratix, ACEX, APEX series | — |
| 封装 | PQFP-100 (20 x 14 mm) | 100-pin PQFP |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Lead-Free / RoHS | Depends on date code; verify per lot | — |
| MSL 等级 | 3 (per JEDEC J-STD-020) | — |
| Programming Cycles | 100 typical (per Altera datasheet) | — |
| Packaging Suffix | 'T' indicates Tape and Reel | — |
| Max DCLK Frequency | [DATA_NEEDED: max DCLK frequency] | — |
| Access Time | [DATA_NEEDED: serial access time] | — |
| Device Type | — | Enhanced Configuration Device |
| Supported FPGAs | — | Stratix, Cyclone, APEX, Mercury (LUT-based) |
| Configuration Schemes | — | PS, PPS, FPP, PPA, JTAG |
| Core Voltage | — | 3.3 V |
| I/O Voltage | — | 1.8 V to 3.3 V |
| Lead Pitch | — | 0.65 mm |
| Compression Support | — | Yes (Stratix / Stratix II) |
| Multi-Device Configuration | — | Yes (daisy chain) |
| Remote Update | — | Yes |