EPC16QC100T vs EPC16QC100DM 对比

详细并排对比 EPC16QC100T 出自 Altera 和 EPC16QC100DM 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16QC100T EPC16QC100DM
品牌 Altera Intel
分类 Memory ICs Memory ICs
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $17.95 $15.85
存储器类型 In-System Programmable Configuration PROM Non-volatile Configuration PROM (NOR flash)
存储容量 16 Mbit —
接口 Serial FPGA configuration + JTAG (IEEE 1149.1) —
Supply Voltage (VCC) 3.3 V —
Programmability In-System Programmable via JTAG —
Daisy-Chain Support Yes (multi-device cascade) —
Data Compression Built-in decompression engine (up to 35% expansion) —
FPGA Compatibility Altera Cyclone, Stratix, ACEX, APEX series —
封装 PQFP-100 (20 x 14 mm) 100-pin PQFP (QFPA)
安装类型 Surface Mount —
工作温度 0C to +70C (commercial) —
Lead-Free / RoHS Depends on date code; verify per lot [DATA_NEEDED: lead-free status]
MSL 等级 3 (per JEDEC J-STD-020) [DATA_NEEDED: MSL rating]
Programming Cycles 100 typical (per Altera datasheet) —
Packaging Suffix 'T' indicates Tape and Reel —
Max DCLK Frequency [DATA_NEEDED: max DCLK frequency] —
Access Time [DATA_NEEDED: serial access time] —
Memory Density — 16 Mbit (2 Mbyte)
Configuration Interface — Serial (SPI-compatible, Altera FPP mode)
Core Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Voltage (VIO) — 2.5 V / 3.3 V selectable
Output Voltage (VPP) — 1.8 V / 2.5 V / 3.3 V selectable
Maximum DCLK Frequency — 40 MHz
Cascadable — Yes (multi-device daisy chain via nCASC)
In-System Programming — Yes (IEEE 1532 / JTAG)
Program/Erase Cycles — [DATA_NEEDED: program/erase cycle endurance]
Data Retention — [DATA_NEEDED: data retention years]
工作温度范围 — -40 C to +85 C (industrial)
Package Code — Q100 + DM suffix
Compatible FPGA Families — Stratix, Cyclone, APEX, ACEX

数据手册与资源

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