EPC20LI20N vs EPC2LI20 对比

详细并排对比 EPC20LI20N 出自 Intel 和 EPC2LI20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC20LI20N EPC2LI20
品牌 Intel Altera
分类 FPGA & CPLD Memory ICs
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $17.50 $5.95
存储器类型 EPROM (UV-erasable, in-system programmable) Flash (in-system programmable)
存储容量 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte) 1.6 Mb (1,572,864 bits)
接口 Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS) —
电源电压 3.3 V (5.0 V compatible variant in same family) —
Configuration Clock Up to 10 MHz —
Target FPGA Families APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA —
封装 20-pin PLCC (9x9 mm, JEDEC MS-018) —
安装类型 Surface Mount (PLCC socket or direct solder) Surface Mount (PLCC socket-compatible)
Programming Interface IEEE 1532 / JTAG (in-system) —
工作温度 -40C to +85C (industrial) -40 C to +85 C (Industrial)
Standby Current [DATA_NEEDED: standby current uA] —
Active Configuration Current [DATA_NEEDED: ICC active mA] —
Programming Voltage [DATA_NEEDED: VPP] —
Programming Cycles [DATA_NEEDED: endurance cycles] —
MSL 等级 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Multi-Device Daisy-Chain Supported via nCASC pin —
Programmable Type — In System Programmable (ISP)
功能 — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
封装 / 外壳 — 20-PLCC (J-lead, 9x9 mm)
Configuration Interface — Serial or Byte-wide (parallel)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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