EPC22LC20 vs EPC2L1696-10F 对比

详细并排对比 EPC22LC20 出自 Intel 和 EPC2L1696-10F 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC22LC20 EPC2L1696-10F
品牌 Intel Altera
分类 FPGA & CPLD Memory ICs
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $4.10 $0.00
功能 In-System Programmable Configuration PROM for SRAM-based FPGAs —
存储容量 1.6 Mbit —
Programmable Type In System Programmable (IEEE 1532 / Jam STAPL) —
Supply Voltage - Low Range 3.0 V to 3.6 V —
Supply Voltage - High Range 4.75 V to 5.25 V —
Supported FPGA Families ACEX 1K, APEX II, APEX 20K, FLEX 10K —
Configuration Interface Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF)
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532) —
封装 / 外壳 20-LCC (J-Lead, 9 x 9 mm) —
安装类型 Surface Mount (PLCC socket compatible) Surface Mount
Packaging Tube —
工作温度 0 C to +70 C (commercial) 0C to +70C (commercial)
Minimum DC Input Voltage -0.3 V —
Input Overshoot Tolerance 7.0 V for <100 mA, <20 ns no-load —
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns no-load —
Lead-Free / RoHS [DATA_NEEDED: lead-free status not in verified data] —
Device Type — Configuration EPROM for SRAM-based LUT FPGAs
Supported Logic Density — 1696 LUTs
Memory Technology — CMOS EEPROM
Supply Voltage (VCC) — 3.3 V
Access Time — 10 ns (speed grade -10)
Maximum DCLK Frequency — [DATA_NEEDED: DCLK max frequency]
Program / Erase Cycles — >= 100,000 cycles
Data Retention — [DATA_NEEDED: data retention years]
In-System Programming — Yes (4-wire JTAG-style interface)
封装 — 20-pin PLCC
MSL 等级 — [DATA_NEEDED: MSL level]
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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