EPC2LC20-V vs EPC2LC20 对比

详细并排对比 EPC2LC20-V 出自 Altera 和 EPC2LC20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2LC20-V EPC2LC20
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.45 $7.20
存储器类型 Configuration PROM (Flash-based, in-system programmable) Non-volatile configuration PROM
Memory Density 1.6 Mbit —
Configuration Interface Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Maximum Configuration Clock 10 MHz —
Supply Voltage VCC 3.3 V 3.0 V to 3.6 V (3.3-V operation)
I/O Tolerance 5 V tolerant on configuration pins —
In-System Programming Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) —
Cascade Support Yes, daisy-chainable for >1.6 Mbit designs Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Operating Temperature Range (V suffix) 0 °C to +70 °C (commercial) —
Package Type 20-pin PLCC (JEDEC MS-018) —
Package Dimensions 9 x 9 mm body, 1.27 mm pitch —
安装类型 Surface Mount (PLCC socket compatible) Surface Mount
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
RoHS 状态 Compliant (per distributor listings) Non-Compliant (original Altera Pb-containing part)
Lead-Free Yes —
存储容量 — 1.6 Mbit
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
ISP Voltage Range — 5.0 V or 3.3 V
封装 — 20-pin PLCC (J-lead, 9x9 mm)
工作温度 — -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

数据手册与资源

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