EPC2LI20J vs EPC1LC20 对比
详细并排对比 EPC2LI20J 出自 Altera 和 EPC1LC20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2LI20J | EPC1LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | Memory ICs | Memory ICs |
| 生命周期状态 | 有效 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $7.95 |
| 存储器类型 | In-System Programmable Configuration PROM (flash) | Non-volatile configuration memory (Flash/EPROM) |
| 存储容量 | 1,695,680 bits (1.6Mb) | — |
| 存储组织 | 65,536 x 1-bit (serial interface) | — |
| 接口 | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | — |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | — |
| ISP Programming Interface | JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (multi-device configuration chain) | — |
| Internal Oscillator | Yes (configures without external clock source) | — |
| 封装 | 20-pin PLCC with J-leads (JEDEC MS-018) | 20-pin PLCC (J-leaded, surface mount) |
| 工作温度 | -40C to +85C (industrial) | [DATA_NEEDED: Operating temperature range] |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Clock (DCLK) | Up to 33 MHz | — |
| Memory Capacity | — | 1 Mbit (1,048,576 bits) |
| 接口类型 | — | Serial configuration interface |
| Maximum DCLK Frequency | — | 8 MHz |
| 电源电压 | — | 3.3 V or 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 / JTAG) |
| Programmable Voltage | — | 5.0 V and 3.3 V ISP |
| Configuration Mode | — | Serial, multi-device daisy-chain capable |
| 引脚数量 | — | 20 |
| 安装类型 | — | Surface Mount |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury |
| JTAG Pins | — | TCK, TMS, TDI, TDO |