EPC2TC32UCAF vs EPC2TC32UCAF48 对比

详细并排对比 EPC2TC32UCAF 出自 Altera 和 EPC2TC32UCAF48 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2TC32UCAF EPC2TC32UCAF48
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $9.95 $14.20
Device Type Configuration PROM (CPLD-style boot memory) —
Memory Density 1.6 Mbit —
Supported FPGA Families Altera APEX, Cyclone, Stratix, FLEX (LUT devices) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.3 V nominal
I/O Logic Levels 3.3 V / 2.5 V compatible —
Configuration Interface FLEX passive serial / passive parallel synchronous / passive parallel asynchronous —
Programming Interface IEEE 1149.1 (JTAG) in-system programmable —
Daisy-Chain Support Yes (via nCASC pin, multi-device FLEX chain) —
Compression Support Altera bitstream compression compatible —
封装 32-pin TQFP (CAF48), 7x7 mm 32-pin TQFP (CAF48 designation per Altera ordering code)
安装类型 Surface Mount Surface Mount
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: commercial 0-70C vs industrial -40-85C variant]
MSL 等级 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL classification]
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: per ordering code; older CAF48 lots were non-RoHS]
Lead-Free [DATA_NEEDED: lead-free status] —
无卤 [DATA_NEEDED: halogen-free status] —
存储容量 — 1.6 Mb
Device Family — EPC2 (Enhanced Configuration Device)
Programmability — In-system programmable (ISP) via JTAG
接口 — 4-wire serial (nCS, DCLK, DATA, nINIT_CONF) + JTAG
FPGA Compatibility — Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX, ACEX, FLEX, MAX 9000)
Cascading — Supported for bitstreams larger than 1.6 Mb
Data Retention — 10 years typical (EEPROM-based)
Programming Cycles — 100 cycles minimum (EEPROM endurance)
Process Technology — CMOS EEPROM

数据手册与资源

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