EPF10K100EQC208-2X vs EPF10K100EQC208-2 对比
详细并排对比 EPF10K100EQC208-2X 出自 Altera 和 EPF10K100EQC208-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPF10K100EQC208-2X - FLEX 10KE FPGA, 100K Gates, 208-PQFP | Altera
EPF10K100EQC208-2X ⚠ 最后一次采购规格对比
| 参数 | EPF10K100EQC208-2X | EPF10K100EQC208-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $59.50 | $155.85 |
| Series | FLEX-10KE | FLEX 10KE |
| Family | FLEX 10KE | — |
| Logic Elements / Cells | 4,992 | — |
| System Gates | 100,000 | — |
| Embedded Memory (EAB RAM) | 49,152 bits | — |
| Number of I/O Pins | 147 | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Number of Embedded Array Blocks (EABs) | 12 | — |
| Supply Voltage (VCCINT) | 2.375 V to 2.625 V (2.5 V nominal) | — |
| Process Technology | 0.22 µm SRAM | — |
| Maximum Internal Frequency (-2 grade) | 250 MHz | — |
| 封装 / 外壳 | 208-BFQFP (PQFP) | 208-BFQFP (PQFP, 28x28 mm) |
| Supplier Device Package | 208-PQFP (28 × 28 mm, 0.5 mm pitch) | — |
| Operating Temperature Grade | Commercial | — |
| Configuration Mode | Passive Serial / Passive Parallel Async | — |
| 安装类型 | Surface Mount | Surface Mount |
| Lead-Free Plating (-X suffix) | Yes (matte-tin, lead-free) | — |
| RoHS 状态 | Compliant (-X suffix) | [DATA_NEEDED: not in provided source data] |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Product Type | — | FPGA (Field Programmable Gate Array) |
| Typical Gate Count | — | 100,000 gates |
| Logic Elements (LEs) | — | 4,992 |
| Total RAM Bits | — | 49,152 bits |
| Logic Array Blocks (LABs) | — | 624 |
| Embedded Array Blocks (EABs) | — | 12 x 2,048 bits |
| Maximum User I/O | — | 147 |
| Supply Voltage - Core (VCCINT) | — | 2.375 V to 2.625 V |
| Supply Voltage - I/O (VCCIO) | — | [DATA_NEEDED: VCCIO range, not in source data] |
| 工作温度 | — | 0 C to +70 C (Commercial) |
| Speed Grade | — | -2 |
| Terminal Form | — | Gull Wing |
| Number of Terminals | — | 208 |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Configuration Method | — | Serial EEPROM / passive serial / JTAG |