EPF10K200SRC240-3N vs EPF10K200SRC240-2X 对比
详细并排对比 EPF10K200SRC240-3N 出自 Intel 和 EPF10K200SRC240-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPF10K200SRC240-2X - FLEX 10K 200K Gates 9984 Cells FPGA | Altera
EPF10K200SRC240-2X ⚠ 最后一次采购规格对比
| 参数 | EPF10K200SRC240-3N | EPF10K200SRC240-2X |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $162.00 | $70.05 |
| Family | FLEX 10KE | FLEX 10KE |
| Typical System Gates | 200,000 | — |
| Logic Elements (LEs) | 9,984 | — |
| Maximum Logic Elements | 9,984 | — |
| Embedded Array Blocks (EABs) | 24 | — |
| Maximum User RAM Bits | 98,304 | — |
| Logic Array Blocks (LABs) | 1,248 | 1248 |
| User I/Os | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions | — |
| Propagation Delay (tPD) | 0.40 ns | — |
| Internal Operating Frequency | 166.67 MHz | — |
| Process Technology | 0.22 µm CMOS SRAM | CMOS |
| Core Supply Voltage | 2.5 V | — |
| MultiVolt I/O Support | 2.5 V and 3.3 V interfaces | — |
| 工作温度 | 0 °C to +70 °C (Commercial) | 0 C to +70 C (Commercial) |
| 封装 | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch | RQFP-240 (240-pin Power Quad Flat Pack, 34.6 x 34.6 mm, 0.5 mm pitch) |
| 安装类型 | Surface Mount | Surface Mount |
| JTAG Support | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) | — |
| Configuration Method | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading | JTAG / Passive Serial (PS) |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| Speed Grade | -3 (commercial) | -2X (industrial, upper-mid speed) |
| Series | — | FLEX 10KS |
| Logic Cells | — | 9984 |
| Equivalent Gates | — | 200,000 |
| Embedded RAM (approx.) | — | 98 Kbits |
| User I/Os (max in family) | — | 470 |
| User I/Os (this package) | — | 182 |
| Propagation Delay | — | 0.4 ns to 0.8 ns |
| Max Internal Frequency | — | 200 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V (banks; 5 V tolerant inputs) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |
| Lead-Free / RoHS | — | [DATA_NEEDED: explicit lead-free status] |
| MSL 等级 | — | [DATA_NEEDED: moisture sensitivity level] |