EPF10K50EFC484-2 vs EPF10K50VFC484-3N 对比

详细并排对比 EPF10K50EFC484-2 出自 Altera 和 EPF10K50VFC484-3N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF10K50EFC484-2 EPF10K50VFC484-3N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $52.75 $24.00
Family FLEX-10KE FLEX-10K
Logic Elements (LEs) 2,880 —
Typical Gates 50,000 50,000
Embedded Memory (Bits) 40,960 —
Embedded Array Blocks (EABs) 12 (each 2,048 bits) 12
Maximum User I/O Pins 220 —
封装 484-ball FineLine BGA (FBGA) 484-FBGA (23 x 23 mm, 1.27 mm pitch)
Process Technology 0.22 micrometer CMOS 0.42 µm CMOS, SRAM-based
Core Voltage 2.5 V —
Internal Frequency 200 MHz 125 MHz
Speed Grade -2 —
工作温度 0 C to +70 C (Commercial) 0 °C to +70 °C (commercial)
JTAG Boundary-Scan IEEE Std. 1149.1-1990 compliant —
PCI Compliance PCI Local Bus Specification Rev. 2.2 at 33/66 MHz (3.3 V); 5.0 V at speed grade -1 —
安装类型 Surface Mount (BGA) Surface Mount (BGA)
Logic Elements — 2,880
Total RAM Bits — 40,960
Logic Array Blocks (LABs) — 10
Maximum User I/Os — 291
Supply Voltage (VCCINT) — 3.0 V to 3.6 V (3.3 V nominal)
I/O Voltage Standards — 5.0 V, 3.3 V, 2.5 V (MultiVolt)
Propagation Delay (per LE) — 0.6 ns
Configuration Modes — Passive Serial, Passive Parallel (Sync/Async), Active Serial, JTAG
JTAG Support — IEEE 1149.1 Boundary Scan
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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