EPF10K50VQC240-3 vs EPF10K50VRC240-1 对比

详细并排对比 EPF10K50VQC240-3 出自 Intel 和 EPF10K50VRC240-1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF10K50VQC240-3 EPF10K50VRC240-1
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $21.50 $130.32
Family FLEX 10K FLEX 10K
Series EPF10K50 —
Typical Gates 50,000 50,000
Logic Elements / Cells 2,880 —
Logic Array Blocks (LABs) 360 —
User I/Os 189 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Supply Voltage (VCCINT) 3.3 V —
Process Technology 0.42 µm CMOS 0.42 µm CMOS
Maximum Internal Frequency 125 MHz —
Propagation Delay (tpd) 0.6 ns —
Package Type 240-pin PQFP (Plastic Quad Flat Pack) —
Package Code FQFP-240 —
工作温度 0 °C to +70 °C (Commercial) 0 °C to +70 °C (Commercial)
安装类型 Surface Mount Surface Mount
Configuration Method SRAM-based, requires external EPC device or MCU —
Speed Grade -3 (mid-tier) —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Compliant
Logic Elements — 2,880
Embedded Memory — 20,480 bits (189 Kb)
User I/O — 274 (max)
Number of I/O Pins — 189
封装 — 240-RQFP Exposed Pad
Pins — 240
Core Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — MultiVolt (2.5 V / 3.3 V / 5 V tolerant)
Internal Frequency (max) — 66.67 MHz
Propagation Delay — 0.6 ns
Logic Family — CMOS
JTAG Support — Yes (IEEE Std 1149.1-1990)
Configuration Interface — JTAG / BitBlaster / ByteBlasterMV / Jam STAPL
Programming Language — Altera MAX+PLUS II / Quartus

数据手册与资源

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