EPF6010ATI100-2 vs EPF6016ATI100-2N 对比

详细并排对比 EPF6010ATI100-2 出自 Altera 和 EPF6016ATI100-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPF6010ATI100-2 EPF6010ATI100-2 - FLEX 6000 10K Gates FPGA | Altera | 100-TQFP

EPF6010ATI100-2 - FLEX 6000 10K Gates FPGA | Altera | 100-TQFP

EPF6010ATI100-2 ⚠ 最后一次采购

规格对比

参数 EPF6010ATI100-2 EPF6016ATI100-2N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $16.20 $14.20
Family FLEX 6000 FLEX 6000
Logic Elements 880 —
Logic Array Blocks (LABs) 88 132 LABs (10 LEs per LAB)
Usable Gates 10,000 —
User I/O Pins 71 —
Maximum Operating Frequency 166.67 MHz —
Process Technology 0.42 µm CMOS 0.42 um CMOS SRAM
Core Voltage 3.3 V —
I/O Voltage 3.3 V (5 V tolerant) —
封装 100-pin TQFP (14×14 mm, 0.5 mm pitch) 100-pin TQFP
Configuration Technology SRAM (volatile) —
工作温度 -40 °C to +85 °C (industrial) 0 C to 85 C (commercial)
Speed Grade -2 —
安装类型 Surface Mount Surface Mount
Terminal Form Gull Wing —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Dedicated Inputs per LAB 4 —
Device Logic Elements — 1,320 LEs
Typical Gate Count — 16,000 gates
User I/Os — 81
Internal Operating Frequency (max) — 166.67 MHz
Core Supply Voltage — 3.3 V
Configuration Method — SRAM, JTAG BST, serial/parallel
I/O Standard Support — 3.3 V LVTTL/LVCMOS, 5.0 V tolerant
Setup Time — 2 ns (typical)
Hold Time — 0 ns (typical)
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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