EPF6016ATI144-2 vs EPF6016AT1144-3N 对比

详细并排对比 EPF6016ATI144-2 出自 Altera 和 EPF6016AT1144-3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF6016ATI144-2 EPF6016AT1144-3N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $9.40 $15.75
Family FLEX 6000 FLEX 6000
Typical Gates 16,000 16,000
Logic Elements 1,320 —
User I/O Pins 117 —
Dedicated Inputs 4 —
最大时钟频率 153 MHz —
Technology 0.42 µm CMOS SRAM —
电源电压 3.0 V to 3.6 V (nominal 3.3 V) —
I/O Tolerance 5.0 V tolerant —
工作温度 -40 °C to 100 °C (Industrial) [DATA_NEEDED: operating temperature range]
封装 TQFP-144 TQFP-144 (T144) 22x22 mm
Terminal Pitch 0.500 mm —
Speed Grade -2 -3 (commercial)
Configuration SRAM, serial EPROM interface —
JTAG Support IEEE 1149.1 boundary-scan —
RoHS 状态 [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status]
Configuration Method OptiFLEX architecture, in-system programmable JTAG / ByteBlasterMV / BitBlaster with external EPC2 or EPC1441 PROM
Device Type — SRAM-based FPGA
Maximum Gates — 24,000
Logic Elements (LEs) — 1,320
Maximum User I/O Pins — 132
Embedded Array Blocks (EABs) — 16
Total RAM Bits — 16,704
Supply Voltage VCCINT — 3.3 V
Supply Voltage VCCIO — 3.3 V (5.0 V tolerant input option)
Process Technology — 0.42 µm CMOS SRAM
安装类型 — Surface Mount
Boundary Scan — IEEE 1149.1 (JTAG) compliant
In-System Programmability — Yes (ISP via JTAG)

数据手册与资源

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