EPM1270TI144C5N vs EPM1270T144C5N 对比

详细并排对比 EPM1270TI144C5N 出自 Intel 和 EPM1270T144C5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM1270TI144C5N EPM1270T144C5N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $9.35 $19.75
Family MAX II MAX II
Device EPM1270 —
Logic Elements / Macro Cells 980 macro cells —
User I/O Count 212 (max for device, 116 used in 144-pin package context) —
Pin-to-Pin Delay (tPD) 6.2 ns —
Maximum Operating Frequency (fMAX) 201.1 MHz —
Technology Node 0.18 µm —
Core Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typ) —
I/O Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Configuration Memory On-chip flash (non-volatile, instant-on) Internal flash (non-volatile, instant-on)
User Flash Memory 8 Kbit (shared with config block) —
工作温度范围 -40 °C to +100 °C (industrial, TI suffix) —
封装 144-pin TQFP TQFP-144 (T144), 22 x 22 mm, 0.5 mm pitch
安装类型 Surface Mount Surface Mount
JTAG / ISP Yes (IEEE 1149.1 boundary scan, in-system programmable) —
RoHS 状态 [DATA_NEEDED: lead-free / RoHS variant not confirmed for -5N TI suffix] Compliant (lead-free)
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 980
Logic Elements (LEs) — 1270
Maximum User I/Os — 212
Number of Logic Array Blocks (LABs) — 127
Process Technology — 0.18 µm
Propagation Delay (tPD) — 6.2 ns
Maximum Internal Frequency — 201.1 MHz
Supply Voltage (Core) — 2.5 V / 3.3 V
Supply Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V
工作温度 — 0 °C to +85 °C (Commercial)
Speed Grade — -5
Programming Interface — JTAG (IEEE 1149.1), In-System Programmable
无卤 — Compliant

数据手册与资源

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