EPM240GT100I5 vs EPM570GT100I5 对比

详细并排对比 EPM240GT100I5 出自 Intel 和 EPM570GT100I5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM240GT100I5 EPM570GT100I5
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $6.10 $4.95
Family MAX II —
Logic Elements 240 —
Equivalent Macrocells 192 —
User I/O Pins 80 —
Propagation Delay (tPD) 7.5 ns 5.4 ns (typ)
User Flash Memory (UFM) 8 Kbits —
Process Technology 0.18 um, 6-layer-metal flash —
工作温度 -40C to +100C (industrial) -40 C to +100 C (Industrial, "I5")
封装 TQFP-100 (GT100) 100-pin TQFP (14x14 mm, 0.5 mm pitch)
Package Body Size 16 mm x 16 mm —
Lead Pitch 0.50 mm —
安装类型 Surface Mount Surface Mount (Gull-wing leads)
Supply Voltage (Core) 3.0 V to 3.6 V (VCCINT) —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Programming Interface JTAG (IEEE 1149.1) / ISP —
RoHS 状态 Compliant Compliant
Series — MAX II
Logic Elements (LE) — 570
Macrocells — 440
Maximum User I/O Pins — 76
Internal Supply Voltage (VCCINT) — 1.71 V to 1.89 V
User I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
User Flash Memory — 8 Kbits
Programmability — In-System Programmable (ISP) via JTAG, non-volatile flash
Configuration Time — Instant-On (< 1 ms, no external PROM required)
Typical Active Current — [DATA_NEEDED: typical active ICC]
Speed Grade — GT (fast)
JTAG Support — IEEE 1149.1 boundary scan
Global Clock Networks — 4

数据手册与资源

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