EPM240T100C4N vs EPM240T100C3N 对比

详细并排对比 EPM240T100C4N 出自 Altera 和 EPM240T100C3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM240T100C4N EPM240T100C3N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $6.10 $9.05
Family MAX II —
Device EPM240 —
Macro Cells 192 —
Logic Elements 240 —
Propagation Delay (tPD) 4.7 ns (max) —
Maximum Frequency 247.5 MHz —
User I/O 80 —
Supply Voltage - Internal 2.5 V / 3.3 V —
I/O Voltage (MultiVolt) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Process Technology 0.18 µm —
Programmable Type In-System Programmable (Flash) —
封装 / 外壳 100-TQFP —
安装类型 Surface Mount Surface Mount
工作温度 0 °C to +85 °C (commercial, 'C' suffix) 0 °C to +85 °C (commercial)
JTAG Support IEEE 1149.1 boundary-scan —
RoHS 状态 Compliant (lead-free, 'N' suffix) Compliant
Series — MAX II
Device Family — MAX II CPLD (EPM240)
Logic Elements (LE) — 240
Macrocells — 192
User I/O Pins — 80
User Flash Memory (UFM) — 8 Kbits
封装 — 100-pin TQFP (14x14 mm)
Configuration Memory — Internal Flash (non-volatile)
Pin-to-Pin Logic Delay (tPD) — 4.4 ns (typical)
Maximum Operating Frequency — 200 MHz (internal oscillator)
Core Supply Voltage (VCCINT) — 3.0 V to 3.6 V
I/O Supply Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V
Programming Interface — JTAG (IEEE 1149.1) / ISP
Quiescent Current (typical) — 35 mA
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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