EPM240T100C4N vs EPM240T100C5N 对比

详细并排对比 EPM240T100C4N 出自 Altera 和 EPM240T100C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM240T100C4N EPM240T100C5N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $6.10 $4.65
Family MAX II MAX II
Device EPM240 —
Macro Cells 192 —
Logic Elements 240 —
Propagation Delay (tPD) 4.7 ns (max) —
Maximum Frequency 247.5 MHz —
User I/O 80 —
Supply Voltage - Internal 2.5 V / 3.3 V —
I/O Voltage (MultiVolt) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Process Technology 0.18 µm 0.18 µm, 6-layer-metal flash
Programmable Type In-System Programmable (Flash) —
封装 / 外壳 100-TQFP —
安装类型 Surface Mount Surface Mount
工作温度 0 °C to +85 °C (commercial, 'C' suffix) 0 °C to +85 °C (commercial, 'C' suffix)
JTAG Support IEEE 1149.1 boundary-scan —
RoHS 状态 Compliant (lead-free, 'N' suffix) Compliant (lead-free)
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements (LEs) — 240
Equivalent Macrocells — 192
On-Chip User Flash — 8 Kbits
Maximum User I/O Pins — 80
Number of I/O Banks — 4
Pin-to-Pin Delay (speed grade 5) — 4.7 ns
Maximum Internal Frequency — 201.1 MHz
Core Supply Voltage (VCCINT) — 2.5 V / 3.3 V
I/O Supply Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
Programming Interface — JTAG (IEEE 1149.1) / ISP
封装 — 100-pin TQFP (T100), 14x14 mm

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