EPM3032ALC44-4N vs EPM3032ALC44-10N 对比

详细并排对比 EPM3032ALC44-4N 出自 Intel 和 EPM3032ALC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3032ALC44-4N EPM3032ALC44-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 不推荐新设计
库存状态 有库存 有库存
单价(USD) $1.32 $0.94
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 32 32
Logic Array Blocks (LABs) 2 2
Usable Gates 600 —
User I/O Pins 34 34
Pin-to-Pin Delay (tPD) 4.5 ns —
Maximum Counter Frequency (fCNT) 227.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
封装 44-pin PLCC (J-Lead) 44-pin PLCC (J-Lead, surface mount)
安装类型 Surface Mount Surface Mount
Programmability EEPROM (non-volatile), IEEE 1149.1 JTAG ISP, IEEE 1532 compliant —
工作温度 [DATA_NEEDED: industrial/commercial grade] [DATA_NEEDED: industrial/commercial range]
RoHS 状态 [DATA_NEEDED: from datasheet] [DATA_NEEDED: compliant or non-compliant]
Product Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 600 gates
Propagation Delay (tPD) — 10 ns
Internal fMAX — 103.1 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O)
Technology — CMOS EEPROM-based
In-System Programmability — Yes, via IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Boundary-Scan Test (BST) — Yes, IEEE 1149.1 compliant

数据手册与资源

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