EPM3032ALC44-7 vs EPM3064ALC44-10 对比

详细并排对比 EPM3032ALC44-7 出自 Altera 和 EPM3064ALC44-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3032ALC44-7 EPM3064ALC44-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.95 $4.12
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements / Macrocells 32 macrocells 64 macrocells
Logic Array Blocks (LABs) 2 —
System Gates 600 —
Number of User I/O Pins 34 —
Global Clocks 2 —
Propagation Delay (tPD1, max) 7.5 ns —
Maximum Internal Frequency (fMAX) 138.9 MHz —
Supply Voltage (VCCINT / VCCIO) 3.3 V —
I/O Tolerant Voltage 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
Program Memory Type EEPROM —
In-System Programming (ISP) Yes - IEEE 1149.1 JTAG —
工作温度 0 °C to +70 °C (Commercial) 0°C to +70°C (commercial)
封装 44-pin PLCC (J-Lead), 16.59 x 16.59 mm, 3.81 mm height 44-PLCC (J-Lead)
安装类型 Surface Mount Surface Mount (PLCC socket compatible)
RoHS 状态 Not Compliant (per Arrow listing) Compliant (lead-free L suffix indicates Pb-free package)
Part Status Obsolete —
ECCN EAR99 —
Number of Logic Array Blocks (LABs) — 4
Usable Gates — 1,250
Maximum User I/O Pins — 34
Supply Voltage (VCCINT) — 3.3 V
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency (fCNT) — 192.3 MHz
Maximum Operating Frequency (fMAX) — [DATA_NEEDED: fMAX internal]
Process Technology — 0.30 µm CMOS EEPROM
Programmability — In-system programmable (JTAG IEEE 1149.1)
MultiVolt I/O — 2.5V / 3.3V / 5.0V interface compatible

数据手册与资源

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