EPM3064ALC44-10N vs EPM3064ATI44-10N 对比

详细并排对比 EPM3064ALC44-10N 出自 Altera 和 EPM3064ATI44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ALC44-10N EPM3064ATI44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $4.25 $3.95
Product Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
User I/O Pins 34 —
Usable Gates 1,250 1250
Propagation Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V —
I/O Bank Voltage (VCCIO) 3.0 V to 3.6 V (MultiVolt) —
Configuration Memory CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) —
封装 44-pin PLCC (LC44) 44-pin TQFP
安装类型 Surface Mount (PLCC socket compatible) Surface Mount
工作温度 [DATA_NEEDED: commercial / industrial grade] -40C to +85C (Industrial, "N" suffix)
RoHS 状态 Compliant Non-Compliant (per digchip datasheet excerpt)
Open-Drain Output Option Yes (per I/O pin) —
Output Slew-Rate Control Programmable —
Family — MAX 3000A
Product Type — CPLD (Complex Programmable Logic Device)
User I/Os — 34
Dedicated Inputs — 4
Logic Blocks — 4
Pin-to-Pin Delay — 10 ns (-10 speed grade)
Maximum Frequency (fMAX) — 100 MHz
Programmable Type — In-System Programmable (EEPROM)
ISP Interface — IEEE Std. 1149.1 (JTAG)
ISP Standard Compliance — IEEE Std. 1532
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V (MultiVolt)
Process Technology — CMOS EEPROM
Boundary-Scan Test — Built-in (JTAG)
Lead-Free Status — Contains Lead (per digchip datasheet excerpt)

数据手册与资源

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