EPM3064ALC44-7N vs EPM3032ALC44-7N 对比

详细并排对比 EPM3064ALC44-7N 出自 Intel 和 EPM3032ALC44-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ALC44-7N EPM3032ALC44-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 不推荐新设计
库存状态 有库存 有库存
单价(USD) $3.95 $1.05
Family MAX 3000A —
Logic IC Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Logic Array Blocks (LABs) 2 —
Usable Gates 1,250 —
Number of User I/O Pins 34 —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Frequency 135.1 MHz —
Core Technology CMOS EEPROM —
Supply Voltage (VCCINT) 3.3 V —
I/O Tolerance 5 V-tolerant —
In-System Programmability Yes (IEEE Std 1149.1 JTAG) —
封装 44-pin PLCC 44-PLCC (J-Lead, 16.59 x 16.59 mm)
安装类型 Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
工作温度 0C to +70C (commercial) 0C to +70C (commercial grade)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Programming Software Quartus II / Quartus Prime (legacy MAX+PLUS II supported) —
Manufacturer — Altera (Intel)
Series — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 32
Logic Gates — 600 usable gates
Propagation Delay (tPD1) — 7.5 ns (max, pin-to-pin)
Internal Counter Frequency (fCNT) — 227.3 MHz (max)
Number of Logic Elements / Blocks — 2 LABs (16 macrocells each)
Number of I/O Pins — 34 usable I/O (44 total package pins)
Number of Dedicated Inputs — 4
Programmable Type — In-System Programmable (ISP) via JTAG (IEEE 1149.1)
存储器类型 — EEPROM (non-volatile, 100 program/erase cycles)
Supply Voltage - Internal (VCCINT) — 3.0 V to 3.6 V (3.3 V typical)
I/O Bank Voltage (VCCIO) — MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant
MSL 等级 — 3 (168 hours)
Process Technology — CMOS EEPROM

数据手册与资源

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