EPM3064ATC100-10NA vs EPM3064ATC-100-10N 对比
详细并排对比 EPM3064ATC100-10NA 出自 Intel 和 EPM3064ATC-100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM3064ATC100-10NA - MAX 3000A CPLD, 64 Macrocells, 10ns, TQFP-100 | Intel (Altera)
EPM3064ATC100-10NA ✓ 量产中规格对比
| 参数 | EPM3064ATC100-10NA | EPM3064ATC-100-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.65 | $2.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| User I/Os | 66 | — |
| Usable Gates | 1,250 | — |
| Logic Array Blocks (LABs) | 4 | 2 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX in MHz] | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| MultiVolt I/O Voltages | 2.5 V / 3.3 V / 5.0 V | — |
| 封装 | TQFP-100 (0.5 mm pitch) | TQFP-100 |
| Configuration Memory | Non-volatile EEPROM | — |
| In-System Programming | IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lead-Free / RoHS | Yes (NA suffix) | — |
| Macro Cells | — | 64 |
| User I/O Pins | — | 66 |
| Usable Gates (min) | — | 600 |
| Usable Gates (typical) | — | 1,250 |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| In-System Programmability | — | Yes (IEEE 1532 / JTAG 1149.1) |
| Programming Interface | — | 4-pin JTAG (TCK/TMS/TDI/TDO) |
| 安装类型 | — | Surface Mount |
| RoHS 状态 | — | Compliant |