EPM3064ATC100-4 vs EPM3064ATI100-10N 对比

详细并排对比 EPM3064ATC100-4 出自 Altera 和 EPM3064ATI100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ATC100-4 EPM3064ATI100-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $5.20 $9.80
Family MAX 3000A MAX 3000A
Device Type CPLD (EEPROM-based) CPLD (Complex Programmable Logic Device)
Macro Cells 64 —
Logic Array Blocks (LABs) 2 4
Usable Gates 1,250 (range 600 to 10,000 across family) 1,250
Maximum User I/O Pins 34 —
Pin-to-Pin Delay (tPD) 4.5 ns 10 ns (-10 speed grade)
Counter Frequency (fCNT) 227.3 MHz —
Internal Performance 222.2 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Voltage (MultiVolt) 2.5 V / 3.3 V / 5.0 V —
In-System Programming Yes (IEEE 1149.1 JTAG) —
Process Technology CMOS EEPROM —
封装 100-pin TQFP 100-pin TQFP (industrial)
安装类型 Surface Mount —
工作温度 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] -40 C to +85 C (industrial)
RoHS 状态 unknown RoHS Non-Compliant
Architecture 5-level Altera MAX —
Programmable Type — In-System Programmable (ISP) via IEEE 1149.1 JTAG
Technology — CMOS EEPROM
Macrocells — 64
User I/O — 66
Supply Voltage (Core / I/O) — 3.3 V
Maximum Internal Frequency — 227.3 MHz (counter)
JTAG (IEEE 1149.1) — Yes
PCI Compliance — PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades)
MultiVolt I/O — Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing
Lead-Free Status — Contains Lead

数据手册与资源

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