EPM3064ATC100-7 vs EPM3064ATC100-7N 对比
详细并排对比 EPM3064ATC100-7 出自 Altera 和 EPM3064ATC100-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 Obsolete规格对比
| 参数 | EPM3064ATC100-7 | EPM3064ATC100-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $3.08 | $6.10 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 1,250 | up to 1,250 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 2 |
| Maximum User I/Os | 66 (in 100-pin TQFP) | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Maximum Internal Counter Frequency | 135.1 MHz | — |
| Supply Voltage - VCCINT (Core) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Technology | CMOS EEPROM | — |
| 封装 | 100-pin TQFP | TQFP-100 |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| In-System Programming (ISP) | Yes, via IEEE 1149.1 JTAG | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| JTAG Boundary Scan | Yes | — |
| Lead Free / RoHS | Compliant (modern shipments) | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| User I/O Pins | — | 66 |
| Propagation Delay (tPD) | — | 7.5 ns (pin-to-pin, -7 speed grade) |
| Maximum Internal Frequency | — | 166.7 MHz (-7 speed grade) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Program Memory Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 |
| RoHS 状态 | — | [DATA_NEEDED: confirmed RoHS status from manufacturer page] |