EPM3064ATC100-7N vs EPM3064ATI100-10N 对比
详细并排对比 EPM3064ATC100-7N 出自 Altera 和 EPM3064ATI100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3064ATC100-7N | EPM3064ATI100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $6.10 | $9.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 4 |
| User I/O Pins | 66 | — |
| Usable Gates | up to 1,250 | 1,250 |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | — |
| Maximum Internal Frequency | 166.7 MHz (-7 speed grade) | 227.3 MHz (counter) |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| Program Memory Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 | — |
| 封装 | TQFP-100 | 100-pin TQFP (industrial) |
| 安装类型 | Surface Mount | — |
| 工作温度 | 0 °C to +70 °C (commercial) | -40 C to +85 C (industrial) |
| RoHS 状态 | [DATA_NEEDED: confirmed RoHS status from manufacturer page] | RoHS Non-Compliant |
| Programmable Type | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM |
| User I/O | — | 66 |
| Supply Voltage (Core / I/O) | — | 3.3 V |
| Pin-to-Pin Delay (tPD) | — | 10 ns (-10 speed grade) |
| JTAG (IEEE 1149.1) | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) |
| MultiVolt I/O | — | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing |
| Lead-Free Status | — | Contains Lead |