EPM3064ATC44-10 vs EPM3064ATI44-10 对比

详细并排对比 EPM3064ATC44-10 出自 Altera 和 EPM3064ATI44-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ATC44-10 EPM3064ATI44-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $4.35 $7.65
Family MAX 3000A MAX 3000A
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 —
Number of Logic Blocks / LABs 4 LABs —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency 227.3 MHz (counter speed) —
Programmable I/Os 34 —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) 3.3 V
I/O Bank Voltage (VCCIO) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Technology CMOS EEPROM, 5 V tolerant I/O —
In-System Programming IEEE Std. 1532 (JTAG) —
Boundary-Scan Support IEEE 1149.1 (JTAG) —
封装 TQFP-44, 10 x 10 mm, 0.8 mm pitch TQFP-44 (10x10 mm, 0.8 mm pitch)
安装类型 Surface Mount Surface Mount
工作温度范围 0C to +70C (commercial) —
RoHS 状态 Non-compliant (legacy Altera, Pb-bearing) Non-Compliant (contains lead, per DigiChip listing)
Product Type — CPLD (Complex Programmable Logic Device)
Programmable Type — In-System Programmable (ISP), EEPROM-based
Number of Macrocells — 64
Number of Logic Array Blocks (LABs) — 4
Number of Usable Gates — 1,250
Number of User I/O Pins — 34
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency — 227.3 MHz
I/O Voltage Tolerance — 5.0 V tolerant (MultiVolt I/O)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532
工作温度 — -40C to +85C (Industrial)
Lead Free Status — Contains Lead
Process Technology — CMOS, EEPROM
Programming Cycles — [DATA_NEEDED: typical program/erase endurance]

数据手册与资源

浏览全部产品 创建 BOM 获取报价