EPM3064ATC44-10N vs EPM3064ALI44-10N 对比

详细并排对比 EPM3064ATC44-10N 出自 Altera 和 EPM3064ALI44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ 量产中

规格对比

参数 EPM3064ATC44-10N EPM3064ALI44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 不推荐新设计
库存状态 有库存 有库存
单价(USD) $5.10 $7.80
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 1250 —
Macro Cells 64 —
User I/O Pins 34 —
Logic Array Blocks (LABs) 4 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 192.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Standard MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) —
Configuration Memory EEPROM (non-volatile) CMOS EEPROM (non-volatile)
In-System Programming IEEE Std. 1532 compliant —
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) compliant —
封装 TQFP-44 (10x10 mm) 44-pin PLCC (J-Lead)
安装类型 Surface Mount Surface Mount (socketable PLCC)
工作温度 0C to +70C (commercial) -40 C to +85 C (Industrial)
RoHS 状态 Compliant —
Pin-Locking Yes (across design iterations) —
Series — MAX 3000A
Programmable Type — In System Programmable (ISP)
Number of Macrocells — 64
Number of I/O — 34
Logic Gates — 1250 gates
Number of Logic Elements/Blocks — 4 LABs
Propagation Delay (tPD) — 10 ns (speed grade -10)
Counter Frequency — up to 227.3 MHz
Supply Voltage - Core — 3.3 V
I/O Logic Level Support — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programming Interface — IEEE Std. 1149.1 JTAG
Lead Free / RoHS Status — Lead Free, RoHS Compliant
Hot-Socketing Support — Yes

数据手册与资源

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