EPM3064ATC44-10N vs EPM3064ATC44-7N 对比

详细并排对比 EPM3064ATC44-10N 出自 Altera 和 EPM3064ATC44-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ 量产中

规格对比

参数 EPM3064ATC44-10N EPM3064ATC44-7N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $5.10 $2.30
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 1250 1,250
Macro Cells 64 64
User I/O Pins 34 34
Logic Array Blocks (LABs) 4 —
Pin-to-Pin Delay (tPD) 10 ns 7.5 ns
Maximum Counter Frequency 192.3 MHz 192.3 MHz (-7 grade)
Supply Voltage (VCCINT) 3.3 V —
I/O Standard MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) —
Configuration Memory EEPROM (non-volatile) —
In-System Programming IEEE Std. 1532 compliant —
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) compliant —
封装 TQFP-44 (10x10 mm) 44-pin TQFP
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) 0°C to +85°C (commercial)
RoHS 状态 Compliant Compliant
Pin-Locking Yes (across design iterations) —
Logic Array Blocks — 2
引脚数 — 44
Speed Grade — -7 (7.5 ns pin-to-pin delay)
Supply Voltage (VCC) — 3.3 V
MultiVolt I/O — 1.8 V / 2.5 V / 3.3 V
Programmability — EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532 compliant
Boundary-Scan Test (BST) — Built-in, JTAG-driven

数据手册与资源

浏览全部产品 创建 BOM 获取报价