EPM3064ATC44-4N vs EPM3064ATC44-10 对比

详细并排对比 EPM3064ATC44-4N 出自 Altera 和 EPM3064ATC44-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ATC44-4N EPM3064ATC44-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $3.45 $4.35
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks 2 —
Number of I/Os 34 —
Dedicated Inputs 4 —
Usable Gates 1,250 1,250
Propagation Delay (tpd) 4.5 ns —
Maximum Counter Frequency 222.2 MHz —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
I/O Supply Voltage (VCCIO) 2.5 V or 3.3 V —
Programmability EEPROM, in-system programmable (JTAG) —
JTAG Support IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) —
工作温度 0C to +70C (commercial) —
封装 44-pin TQFP TQFP-44, 10 x 10 mm, 0.8 mm pitch
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: rohs status] Non-compliant (legacy Altera, Pb-bearing)
Logic Elements / Macrocells — 64 macrocells
Number of Logic Blocks / LABs — 4 LABs
Propagation Delay (tPD) — 10 ns
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
I/O Bank Voltage (VCCIO) — MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Technology — CMOS EEPROM, 5 V tolerant I/O
In-System Programming — IEEE Std. 1532 (JTAG)
Boundary-Scan Support — IEEE 1149.1 (JTAG)
工作温度范围 — 0C to +70C (commercial)

数据手册与资源

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