EPM3064ATI100-10 vs EPM3064ATC100-10N 对比
详细并排对比 EPM3064ATI100-10 出自 Intel 和 EPM3064ATC100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3064ATI100-10 | EPM3064ATC100-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $6.80 | $2.43 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of User I/Os | 66 | — |
| Usable Gates | 1,250 | 1,250 |
| 电源电压 | 3.3 V | — |
| Speed Grade | -10 (10 ns pin-to-pin) | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| 封装 | 100-pin TQFP | 100-pin TQFP |
| 安装类型 | Surface Mount | Surface Mount |
| Operating Temperature Grade | Industrial | — |
| Lead Free Status | Contains Lead | — |
| RoHS 状态 | Non-Compliant | Compliant (lead-free) |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| In-System Programmability | — | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |
| 工作温度 | — | 0C to +70C (commercial) |