EPM3064ATI100-10N vs EPM3064ATC100-4 对比
详细并排对比 EPM3064ATI100-10N 出自 Altera 和 EPM3064ATC100-4 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3064ATI100-10N | EPM3064ATC100-4 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.80 | $5.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EEPROM-based) |
| Programmable Type | In-System Programmable (ISP) via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM | — |
| Usable Gates | 1,250 | 1,250 (range 600 to 10,000 across family) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | 2 |
| User I/O | 66 | — |
| Supply Voltage (Core / I/O) | 3.3 V | — |
| Pin-to-Pin Delay (tPD) | 10 ns (-10 speed grade) | 4.5 ns |
| Maximum Internal Frequency | 227.3 MHz (counter) | — |
| 封装 | 100-pin TQFP (industrial) | 100-pin TQFP |
| 工作温度 | -40 C to +85 C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] |
| JTAG (IEEE 1149.1) | Yes | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) | — |
| MultiVolt I/O | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing | — |
| Lead-Free Status | Contains Lead | — |
| RoHS 状态 | RoHS Non-Compliant | unknown |
| Macro Cells | — | 64 |
| Maximum User I/O Pins | — | 34 |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Internal Performance | — | 222.2 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM |
| 安装类型 | — | Surface Mount |
| Architecture | — | 5-level Altera MAX |