EPM3064ATI44-10N vs EPM3064ALI44-10N 对比

详细并排对比 EPM3064ATI44-10N 出自 Altera 和 EPM3064ALI44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ATI44-10N EPM3064ALI44-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $3.95 $7.80
Family MAX 3000A —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Usable Gates 1250 —
User I/Os 34 —
Dedicated Inputs 4 —
Logic Blocks 4 —
Pin-to-Pin Delay 10 ns (-10 speed grade) —
Maximum Frequency (fMAX) 100 MHz —
Programmable Type In-System Programmable (EEPROM) In System Programmable (ISP)
ISP Interface IEEE Std. 1149.1 (JTAG) —
ISP Standard Compliance IEEE Std. 1532 —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V (MultiVolt) —
工作温度 -40C to +85C (Industrial, "N" suffix) -40 C to +85 C (Industrial)
封装 44-pin TQFP 44-pin PLCC (J-Lead)
Process Technology CMOS EEPROM —
Boundary-Scan Test Built-in (JTAG) —
安装类型 Surface Mount Surface Mount (socketable PLCC)
Lead-Free Status Contains Lead (per digchip datasheet excerpt) —
RoHS 状态 Non-Compliant (per digchip datasheet excerpt) —
Series — MAX 3000A
Number of Macrocells — 64
Number of I/O — 34
Logic Gates — 1250 gates
Number of Logic Elements/Blocks — 4 LABs
Propagation Delay (tPD) — 10 ns (speed grade -10)
Counter Frequency — up to 227.3 MHz
Supply Voltage - Core — 3.3 V
I/O Logic Level Support — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programming Interface — IEEE Std. 1149.1 JTAG
Lead Free / RoHS Status — Lead Free, RoHS Compliant
Hot-Socketing Support — Yes
Configuration Memory — CMOS EEPROM (non-volatile)

数据手册与资源

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