EPM3128ATC144-5 vs EPM3128ATC144-5N 对比
详细并排对比 EPM3128ATC144-5 出自 Altera 和 EPM3128ATC144-5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3128ATC144-5 | EPM3128ATC144-5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.85 | $13.75 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS | CMOS |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Number of User I/Os | 96 | — |
| Device System Gates | 2500 | — |
| Product Terms per Macrocell | 32 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency | 192.3 MHz | — |
| Number of Global Clocks | 2 | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| Supply Voltage (Core) | 3.3 V | 3.3 V |
| Multi-Volt I/O Voltage | 2.5 V / 3.3 V / 5.0 V tolerant | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | Yes (3.3-V via JTAG) |
| JTAG / IEEE 1149.1 | Yes (boundary-scan + ISP) | — |
| 工作温度 | 0C to +70C (Commercial) | 0C to 70C (Commercial) |
| 封装 | TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm) | 144-pin TQFP (20x20 mm) |
| Process Technology | 0.30 um CMOS EEPROM, 4 metal layers | — |
| RoHS 状态 | Not Compliant (per Arrow distributor listing) | Compliant (lead-free) |
| ECCN | EAR99 | — |
| HTS Code | 8542.31.00.55 | — |
| Macrocells | — | 128 |
| Usable Gates | — | 2500 |
| User I/O | — | 96 |
| Pin-to-Pin Logic Delay | — | 5 ns |
| Counter Frequency | — | up to 227.3 MHz |
| I/O Logic Levels Supported | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| JTAG Boundary Scan | — | IEEE Std 1149.1 compliant |
| 安装类型 | — | Surface Mount |