EPM3128ATI100-5N vs EPM3128ATC100-5 对比

详细并排对比 EPM3128ATI100-5N 出自 Intel 和 EPM3128ATC100-5 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATI100-5N EPM3128ATC100-5
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $11.45 $15.43
Family MAX 3000A CPLD - MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 128 128
Logic Array Blocks (LABs) 8 (16 macrocells per LAB) —
User I/O Pins 80 —
Pin-to-Pin Delay (tPD) 5.0 ns —
Supply Voltage (VCCINT) 3.3 V —
I/O Standard 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs —
Programming Method In-System Programmable via IEEE Std. 1532 (JTAG) —
工作温度 -40C to +85C (Industrial) 0 °C to 70 °C (Commercial)
封装 100-pin TQFP 100-pin TQFP (Fine Line)
安装类型 Surface Mount Surface Mount
Configuration Memory Non-volatile EEPROM —
JTAG Support IEEE 1149.1 boundary scan —
RoHS 状态 Compliant (lead-free TQFP package) [DATA_NEEDED: RoHS status]
Series — MAX 3000A
Usable Gates — 2,500
User I/Os — 80
Dedicated Inputs — 4
Pin-to-Pin Delay (tpd) — 5 ns (commercial); 7.5 ns
Maximum Frequency (fCNT) — 192.3 MHz
Supply Voltage (VCCINT/VCCIO) — 3.3 V
Output Drive Voltage — 2.5 V or 3.3 V (programmable)
Input Tolerance — 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM
In-System Programmability — Yes, IEEE Std. 1532 compliant
JTAG Boundary Scan — Yes, IEEE Std. 1149.1
Logic Family — CMOS
Process Technology — CMOS EEPROM

数据手册与资源

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