EPM3256AFC256-10N vs EPM3512AFC256-10 对比
详细并排对比 EPM3256AFC256-10N 出自 Altera 和 EPM3512AFC256-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3256AFC256-10N | EPM3512AFC256-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $25.95 | $17.50 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 5,000 gates | 10,000 |
| Macrocells | 256 | 512 |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | 87 MHz |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| 封装 | 256-pin FineLine BGA | 256-pin FBGA |
| Logic Family | CMOS | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| 工作温度 | 0 C to 70 C (commercial) | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| 工作温度范围 | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| 引脚数量 | — | 256 |
| 安装类型 | — | Surface Mount |
| RoHS 状态 | — | unknown |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |